Many electronic circuits, typically microprocessor based circuits, are required to store digital information either temporarily or permanently, and must further access the information quickly. Furthermore, it is common for many electronic circuits to require both temporary and permanent data storage in the same system. The number of bits required for storage and thus the number of memory cells may vary considerably from system to system. Because the number of storage bits required may be large, it is advantageous to increase the density of memory bits for a given area.
Application Specific Integrated Circuits (ASICs) is an example of an application that often requires different combinations of memory, and each type of memory in different amounts. The memories are typically each placed in separate locations on the chip, each being a stand alone memory system. Typically each memory consists of memory cells arrayed in an x-y array having row decoders located along the y axis to provide word decoding and having column decoders located along the x axis for providing bit decoding. The memory cells of each memory array each have an x and y pitch (width and height of each cell, respectively) which are typically matched to the y pitch of the row decoders and to the x pitch of the column decoders, respectively.
Since the array of the memory cells normally takes up the majority of area, the memory cell is designed first to be as compact as possible both in the x and y pitches. The row and column decoders are then designed to match the already determined x and y pitches of the memory cells. This is an efficient and effective method of design, especially in large memories. In ASIC applications, where the number of memory cells generally are not large, the row and column decoders take a proportionately larger amount of area. Furthermore, Random Access Memories (RAM) cells are typically larger than Electrically Programmable Read Only Memory (EPROM) cells which in turn are larger than Read Only Memory (ROM) cells.
ASIC applications which require differnt types of memories in varying amounts, often are not required to access the different memories on the same clock cycle (or asynchronously). The different types of memories may then be accessd individually, usually putting their addressed contents onto a bus. In effet the row decoders, and in some cases the column decoders of each memory array are redundant and moreover require a significant amount of area. If the smaller memory cells were designed to be pitched matched to the largest memory cell, then the row and/or column decoders could be shared. This is especially efficient when there are smaller amounts of the smaller memory cells.
Pitched matched arrays may be configured using conventional Computer Aided Design (CAD) techniques. However hierarchical structured design methods, and more particularly, silicon compilers, having made it more efficient in laying out such an integrated circuit design. The silicon compiler may take a high level description of the system and convert it into a parameterized layout of the circuit. Although the initial preparation of the design software may consume a lenghty time period, subsequent circuit design for multiple circuits requires substantially less time. Once the x and y pitches of the largest memory cell are determined, these parameters may be used to quickly layout other pitch matched memories.
Thus, what is needed is a combined memory system which merges pitched matched arrays of different types of memory, for example, Random Access Memory (RAM), Read Only Memory (ROM), Electrically Programmable ROM (EPROM), or some combination thereof.